Siam Umar Hussain

I am Siam Umar Hussain, a PhD student at the Department of Electrical and Computer Engineering at University of California, San Diego. I am working with Professor Farinaz Koushanfar at the ACES Lab.

My research focus is enabling data-intensive systems with provable privacy guarantee in practical settings. Following are some of my research highlights.

Efficient and scalable framework for secure Multi-Party Computation (MPC). TinyGarble [15] - Yao’s Garbled Circuit (GC) - provides a logic synthesis library to generate GC optimized Boolean circuit using HDL synthesis tools. It thus allows SFE to benefit from more than forty years of research on HDL synthesis. I recently developed TinyGarble2.0 [3], a C++ framework for GC execution in both honest-but-curious and malicious security models. It includes a library for Convolutional Neural Networks (CNN) inference. My recent work includes an automated mixed protocol framework incorporating GC, Arithmetic Sharing (AS), and Homomorphic Encryption (HE).
Co-optimization of cryptographic protocols and privacy-sensitive applications. I have developed a number of MPC-based applications including authentication with noisy keys (fingerprints) [9], secure localization [12, 10], and k-Nearest Neighbor Search (k-NNS) on private data [14]. My recent results include mixed protocol system for oblivious Machine Learning (ML) inference through Crypto-ML co-optimization (3-7× run-time improvement over state-of-the-art). The proposed system supports both generic CNN as well as specialized versions like Binarized Neural Network (BNN)[1].
Accelerators for cryptographic protocols. I have developed, FASE [6] - the fastest FPGA accelerator for GC. It outperforms the previous work by a minimum of 110 times in terms of throughput per core. I have also developed MAXelerator [11] - an FPGA accelerator for GC customized for matrix multiplication. My recent work includes acceleration of Oblivious Transfer (OT) and HE.
Hardware security primitives. I implemented a Built-In Self-Test (BIST) [13, 16] scheme for runtime monitoring of True Random Number Generators (TRNG) and Physical Unclonable Functions (PUF) on FPGA. Our PUF design based on Programmable Delay Logic (PDL) won in the categories: most unique PUF, most Stable PUF (Aging), and most efficient PUF at CSI CyberSEED.