Education

PhD in Computer Engineering
CGPA: 4.00/4.00
Advisor: Professor Farinaz Koushanfar
Courses: Optimization and Acceleration of Deep Learning on Hardware


MS in Computer Engineering
CGPA: 3.83/4.00
Thesis: “P3: Privacy Preserving Positioning for Smart Automotive Systems”
Advisor: Professor Farinaz Koushanfar
Courses: Design & Analysis of Algorithms, Computer Systems Architecture, Introduction to Random Processes, Advanced Digital Design & Implementation, Advanced VLSI Design, Embedded HW Systems Security, High Performance Computer Architecture, Innovation Lab for Mobile Health


BSc in Electrical & Electronic Engineering
CGPA: 3.94/4.00
Thesis: “UWB microwave imaging via modified beamforming for early detection of breast cancer”
Advisor: Professor ABM Harunur Rashid
Courses: Analog Integrated Circuit, VLSI I and II, Electronics I and II, Digital Electronics, Microprocessor & Interfacing, Engineering Electromagnetics, Electric Properties of Materials, Solid State Devices, Compound semiconductor & Hetero-junction devices, Communication Theory, Continuous Signals and Linear Systems, DSP I and II, Mobile Cellular Communication, Telecommunication Engineering

Projects

• C++ Framework for Scalable and Efficient Privacy-Preserving Computation through GC [3]:
  • A GC-execution back-end with all recent optimizations.
  • A C++library with common arithmetic and logical building blocks.
  • A C++library for privacy-preserving CNN inference.
  • Scalable execution through secure transfer of shares.
  • Execution of the same program in either of honest-but-curious or malicious security models.
• Oblivious Machine Learning (ML) inference
  • Crypto-ML co-optimization for efficient mixed protocol solution
  • Fast execution in the amortized setting (3-7× run-time improvement over state-of-the-art).
  • Supports both generic CNN as well as specialized versions like Binarized Neural Network (BNN)[1]
• Privacy-Preserving Applications:
  • Authentication with noisy keys [9].
  • Secure localization [12, 10].
  • k-Nearest Neighbor Search (k-NNS) on private data [14].
• FPGA Acceleration of Secure Function Evaluation with Yao’s GC Protocol: I developed two accelerators
  • FASE supports any generic function. It is minimum 110× faster than previous work [6].
  • MAXelerator is customized for matrix multiplication. It is 4× faster than FASE [11].
• Circuit Compilation for Yao’s GC with Industrial Logic Synthesis Tools [15]:
  • Designed synthesis libraries and optimization strategies to compile circuits optimized for the GC protocol.
  • Reduced the cost by up to 84% compared to previous work. Currently the most efficient GC circuit generation tool.
• On-chip Test of True Random Number Generators (TRNG) and Physical Unclonable Functions (PUF) [13, 16]:
  • Built-In-Self-Test scheme on FPGA for online evaluation, incorporates seven tests from the NIST test suit.
  • Implemented and evaluated two TRNGs and one PUF architectures.

Work Experience

Graduate Technical Intern
Projects: Efficient and scalable privacy-preserving computation; hardware acceleration of GC; mixed protocol framework for privacy-preserving computation; practical privacy-sensitive systems.


Research Intern
Projects: Efficient interactive Zero Knowledge Proof (ZKP) via MPC.


Graduate Technical Intern
Projects: A C++ framework for scalable and efficient privacy-preserving computation through the Yao's Garbled Circuit (GC) protocol in both honest-but-curious and malicious security models. The framework includes parameterized implementations of basic building blocks of Convolutional Neural Networks (CNN).


Hardware Engineering Intern
Duties: Design of a bridge between the DRAM memory controller running the QFI (Qualcomm standard) protocol and the physical system running the DFI (industry standard) protocol.


Hardware Engineering Intern
Duties: Enhancement of two Samsung mobile platforms - MMP and SGP with region-specific features.


Graduate Research Assistant
Projects: Design, implementation, and evaluation of Hardware security primitives; Efficient and scalable privacy-preserving computation; secure localization.

Technical Skills

Language: C/C++, Verilog, MATLAB, Python, Java, VHDL, Assembly (Intel x86), HTML, CSS
Technologies: SPICE, Cadence, Yosys, Synopsys Design Compiler, Xilinx ISE, Vivado HLx, PlanAhead, FPGA Editor, Quartus, ModelSim, Git, Visual Studio, Eclipse, Android Studio

6 years experience in Programming C/C++:

• Developed TinyGarble2, a C++ framework for secure function evaluation based on Yao’s Garbled Circuit (GC) [3].
• Privacy-preserving localization for smart automotive systems [12, 10]
• Worked as a Software Engineer for 18-months at Samsung Bangladesh R&D Center where I developed region specific models based on Samsung mobile platforms.

6 months experience in Programming Java:

• PhaseGear: An embedded system on a glove to detect workout and provide feedback on wrong form, along with an Android app as the interface.

6 years experience in Digital Design (Verilog/System Verilog):

• Design/Implementation of True Random Number Generator and Physical Unclonable Function on FPGA [13, 16].
• HDL synthesis library to generate GC optimized Boolean circuit using Synopsys DC [15].
• HDL implementation of triangle localization and k-NNS [12, 10, 14].
• Implementation of beamforming algorithm for breast cancer detection on FPGA [17].
• Implementation of efficient division algorithm in hardware

2 years experience in Design Verification:

• Design and implementation of Built-In-Self-Test scheme for online evaluation of True Random Number Generator and Physical Unclonable Function on FPGA [13, 16]

2 years experience in Physical Design:

• Design/Implementation of True Random Number Generator and Physical Unclonable Function on FPGA [13, 16].

Awards

• Best project award in Microsoft Research Private AI Bootcamp, 2019.
• Awards in the most unique, most stable (Aging), and most efficient PUF categories at Hardware Challenge of CSI CyberSEED, 2014.

Publications

1. S. U. Hussain, M. Samragh, X. Zhang, K. Huang and F. Koushanfar, On the Application of Binary Neural Networks in Oblivious Inference, IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR) Workshops, May, 2021.
   
2. S. U. Hussain, S. M. Riazi, and F. Koushanfar, The Fusion of Secure Function Evaluation and Logic Synthesis, IEEE Security & Privacy, March, 2021.
   
3. S. U. Hussain, B. Li, F. Koushanfar, and R. Cammarota, TinyGarble2: Smart, Efficient, and Scalable Yao’s Garble Circuit, Workshop on Privacy-Preserving Machine Learning in Practice (PPMLP), November, 2020.
   
4. R. Cammarota et. al., Trustworthy AI Inference Systems: An Industry Research View, Workshop on Privacy-Preserving Machine Learning in Practice (PPMLP), November, 2020.
   
5. H. Chen, S. U. Hussain, F. Boemer, E. Stapf, A. - R. Sadeghi, F. Koushanfar, and R. Cammarota, Developing Privacy-Preserving AI Systems: The Lessons Learned, Design Automation Conference (DAC), July, 2020.
   
6. S. U. Hussain and F. Koushanfar, FASE: FPGA Acceleration of Secure Function Evaluation, Field-Programmable Custom Computing Machines (FCCM), April, 2019.
   
7. S. M. Riazi, M. Javaheripi, S. U. Hussain and F. Koushanfar, MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation, Hardware Oriented Security and Trust (HOST), June, 2019.
   
8. E. Songhori, S. M. Riazi, S. U. Hussain, and F. Koushanfar, ARM2GC: Succinct Garbled Processor for Secure Computation, Design Automation Conference (DAC), June, 2018.
   
9. S. U. Hussain, S. M. Riazi, and F. Koushanfar, SHAIP: Secure Hamming Distance for Authentication of Intrinsic PUFs, ACM Transactions on Design Automation of Electronic Systems (TODAES), 23.6, p.75, 2018.
   
10. S. U. Hussain and F. Koushanfar, P3: Privacy Preserving Positioning for Smart Automotive Systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), 23.6, p.79, 2018.
    
11. S. U. Hussain, B. D. Rouhani, M. Ghasemzadeh, and F. Koushanfar, MAXelerator: FPGA Accelerator for Privacy Preserving Multiply-Accumulate (MAC) on Cloud Servers, Design Automation Conference (DAC), July, 2018.
    
12. S. U. Hussain, and F. Koushanfar, Privacy Preserving Localization for Smart Automotive Systems, Design Automation Conference (DAC), June, 2016.
    
13. S. U. Hussain, M. Majzoobi, and F. Koushanfar, A Built-In-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators, IEEE Transactions on Multi-Scale Computing Systems, vol. 2, issue 99, January, 2016.
    
14. E. Songhori , S. U. Hussain, A. - R. Sadeghi, and F. Koushanfar, Compacting privacy-preserving k-nearest neighbor search using logic synthesis, Design Automation Conference (DAC), June, 2015.
    
15. E. Songhori , S. U. Hussain, A. - R. Sadeghi, T. Schneider, and F. Koushanfar, TinyGarble: Highly Compressed and Scalable Sequential Garbled Circuits, IEEE Symposium on Security and Privacy (S&P), May, 2015.
    
16. S. U. Hussain, S. Yellapantula, M. Majzoobi, and F. Koushanfar, BIST-PUF: Online, Hardware-based Evaluation of Physically Unclonable Circuit Identifiers, International Conference on Computer-Aided Design, November, 2014.
    
17. Paul, M.K., Sagar, M.A.K., Hussain, S.U. & Rashid, A.B.M.H., UWB microwave imaging via modified beamforming for early detection of breast cancer, In IEEE International Conference on Electrical and Computer Engineering (ICECE), December, 2010.